The invention relates to a program-controlled data processor, more particularly a data switching system using a plurality of processing units and a plurality of memory banks and at least one storage input/output control governing the traffic between the processing units and the memory banks via communication channels and containing an input and output circuit for the information as well as an input and output control establishing the links between associated processing units and memory banks, wherein a plurality of communication paths for information input and output are provided in the input and output circuits.
The construction details of the elemental units of such a system are described in U.S. Pat. No. 3,792,439. The block diagram of the system proposed herein illustrates in FIG. 1 the processing units VE with their own operating sequence controls governed by wired instructions and/or instructions located in the storage unit. These processing units are similar to other processing units known in the art. The operating sequence controls are connected with a storage input/output control SEAS over information channels a and control channels b. Access to the working storage takes place in cycles, that is to say, for each cycle to be allotted it is decided which processing units shall have access to the working storage. Since the working storage shall have a large capacity and a minimum cycle time it is made up of a number of memory banks SB, each of which combines the storage medium and the memory operation control into a logic functional unit. The construction of the memory is apparent from FIGS. 4a and 4b of the U.S. Pat. No. 3,792,439 and from the description therein. These memory banks are likewise connected with the storage input/output control SEAS over information channels a and control channels b. The storage input/output control SEAS comprises an input circuit ES to which the information lines a leading to the processing units VE and memory banks SB are connected and by means of which the storage word address, the operation code and the storage word are read into the storage. The paths between the various processing units VE and memory banks SB in the input circuit ES are switched by the input control EAS which is connected with the processing units VE and memory banks SB over control lines b. The signals for the cycle request, the special priority and the memory bank address are transmitted over the control lines b between the processing units and the input control EAS. The information output takes place over an output circuit AS which is likewise connected with the memory banks SB and the processing units VE over information lines a. The paths in the output circuit AS are switched by the output control AAS which causes, among other things, the transfer of the storage output report to the processing units over control lines. Input control EAS and output control AAS are connected by a register R in which the condition of the memory banks SB, that is to say, the coordination between processing units VE and memory banks SB is stored. The storage input/output control SEAS now has the task of selecting the processing valve VE requesting storage cycles and the memory banks SB making output requests dependent upon the priority thereof. In the proposed storage input/output control SEAS it is possible to run several memory bank cycles concurrently, whereby the effective cycle time of each memory bank equals a whole multiple of the processing time of the storage input/output control. This processing time of the storage input/output control SEAS will hereinafter be referred to as an operating interval.
The shorter this operating interval, the more memory bank cycles can be initiated by the storage input/output control SEAS within a given period of time. Four parallel information paths are constructed both in the input circuit ES and in the output circuit AS of the storage input/output control SEAS for connecting the processing units to the memory banks and the memory banks to the processing units, respectively. These paths can be used by individual processing units and memory banks or by pairs of processing units or pairs of memory banks if identical processing units or memory banks operate in a parallel mode. These parallel information paths are shown in FIG. 6 of U.S. Pat. No. 3,792,439 and in the input circuit (ES) shown in FIG. 2 herein as paths PA, PB, PC and PD. The processing units and the memory banks are each combined into four groups in accordance with the number of parallel information paths through the storage input/output control for the processing of the storage cycle requests of the processing units VE or output requests of the memory banks SB and for the associated switching of the information. The groups of the processing units VE and of the memory banks SB are connected both in the input and output circuit by a space-division circuit (four parallel paths). The above arrangement for grouping the processing units VE and the memory banks SB is shown in U.S. Pat. No. 3,792,439. A central comparator is assigned to every two of these groups of processing units in the input circuit and every two of these groups of memory banks in the output circuit. These central comparators enable the processing units and/or the memory banks to operate in the parallel mode. The operation of these central comparators is in accordance with the operating interval of the storage input/output control. During this interval, only one comparison process is possible for a given pair of parallel processing units or memory banks. Thus, the operation of these common comparators is staggered in time and concurrent demands made by the processing units and/or memory banks of these common comparators are processed in succession. In this way the storage input/output control can be operated in each successive case with increased reliability and without cross-connecting of individual comparators assigned to the processing units or memory banks. Parallel operation of processing units is possible between the groups A and B (A1-B1, A2-B2, A3-B3, A4-B4) and between the groups C and D (C1-D1, C2-D2, C3-D3, C4-D4), parallel operation of memory banks between the groups W and X (W1-X1, W2-X2, W3-X3, W4-X4), and between the groups Y and Z (Y1-Z1, Y2-Z2, Y3-Z3, Y4-Z4). An example of the structural details of the information input circuit ES is shown in FIG. 6 of the U.S. Pat. No. 3,792,439.
As shown by U.S. Pat. No. 3,792,439, it is well known to select various processing units VE or memory banks SB for connection consideration being given to their order of preference and destination. However, under these prior known systems, if input requests from processing units and/or several output requests from memory banks are made upon previously known storage input/output control systems concurrently, this storage input/output control operates inefficiently, that is to say, it operates at an excessively low operating speed. One object of the invention is to modify these previously known storage input/output control systems such that a higher operating speed is achieved.